SiC gate drive control with trench FETs from high dV\dT at drain source

ABSTRACT

A switching circuit can help reduce electrical feedback ringing at a gate terminal of a transistor. The switching circuit can include a transistor circuit to switch an electrical signal and a control circuit to provide an actuation signal to the gate terminal of the transistor device. The switching circuit can also include a booster circuit that is disposed between the control circuit and the gate terminal of the transistor device. The booster circuit can be configured to detect a signal from the control circuit to turn off the transistor device and, responsive to the detected signal, drive a current into the gate terminal of the transistor device for a specified span of time before the transistor device turns off.

FIELD OF THE DISCLOSURE

This document pertains generally, but not by way of limitation, to thecontrol of high voltage switching devices to reduce ringing caused byfeedback signals generated by high speed switching.

BACKGROUND

Electronic systems that incorporate high voltage switching circuits,such as switched power converters, can use switching devices tocondition electrical power for use by other circuits. Such switchingdevices can include field effect transistors (FETs), such as siliconcarbide field effect transistors (SiC FETs), that are configured tocontrollably switch large voltages at high speeds. In an example, a SiCFET can be driven by a gate driver circuit to switch a high voltagesignal (e.g., a signal having a voltage magnitude of at greater than1000 volts (V) between the drain and source terminals of the transistorwith switching times that are on the order of a few nanoseconds (ns) orfaster. An example of a SiC FET includes a trench FET, such as describedin U.S. Pat. No. 7,595,238B2 to Takashi Tsuji which issued Sep. 29,2009.

SUMMARY OF THE DISCLOSURE

An example of the present disclosure includes a switching circuit toreduce electrical feedback ringing at a gate terminal of a transistor.The switching circuit can include a transistor circuit to switch anelectrical signal, a control circuit to provide an actuation signal tothe gate terminal of the transistor device, and a booster circuit thatis disposed between the control circuit and the gate terminal of thetransistor device. The booster circuit can be arranged to detect asignal from the control circuit to turn off the transistor device and,responsive to the detected signal, drive a current into the gateterminal of the transistor device for a specified span of time beforethe transistor device turns off.

Another example of the present disclosure includes method forcontrolling a field effect transistor (FET) to reduce electricalfeedback ringing a gate terminal of the FET. The method can includedetecting a control signal to switch the FET from an on-state to anoff-state and driving, responsive to detecting the control signal, afirst current into the gate terminal while a voltage on the gateterminal is greater than an indicated threshold voltage. The method canfurther include sinking a second current from the gate terminal to turnoff the FET when the voltage on the gate terminal falls below thethreshold voltage.

A further example of present disclosure includes a system for reducingelectrical feedback ringing a gate terminal of a FET. The system caninclude means for detecting a control signal to switch the FET from anon-state to an off-state and means for driving, responsive to detectingthe control signal, a first current into the gate terminal while avoltage on the gate terminal is at least as high as an indicatedthreshold voltage. The system can further include means for sinking asecond current from the gate terminal to turn off the FET when thevoltage on the gate terminal falls below the threshold voltage.

This summary is intended to provide an overview of subject matter of thepresent patent application. It is not intended to provide an exclusiveor exhaustive explanation of the embodiments of the invention. Thedetailed description is included to provide further information aboutthe present patent application.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, which are not necessarily drawn to scale, like numeralsmay describe similar components in different views. Like numerals havingdifferent letter suffixes may represent different instances of similarcomponents. The drawings illustrate generally, by way of example, butnot by way of limitation, various embodiments discussed in the presentdocument.

FIG. 1 is a block diagram illustrating an example of a circuit that isconfigured to attenuate ringing caused by feedback of an electricalsignal at a transistor.

FIGS. 2A and 2B are graphs illustrating an example of ringing caused byfeedback of an electrical signal at a transistor from a drain terminalto a gate terminal.

FIGS. 3A, 3B, and 3C are graphs illustrating an example of attenuatedringing at a transistor.

FIG. 4 is a block diagram illustrating an example of a device thatincludes a switching circuit that is configured to reduce ringing causedby feedback of an electrical signal at a transistor.

FIG. 5 is a flow chart illustrating an example of a method of operatinga circuit to attenuate ringing caused by feedback of an electricalsignal at a transistor.

DETAILED DESCRIPTION

The present disclosure includes a gate driver circuit that is configuredto reduce ringing at the gate of a power transistor, such as SiC FET,during high speed switching of large voltage signals. The disclosed gatedriver reduces ringing feedback from the drain to the gate of the SiCFET by injecting a current into the gate of the transistor for a shortspan of time after the control circuit of the gate driver generates anactuation signal to drive the voltage on the gate low, such as to turnthe transistor off. The disclosed gate driver improves on other gatedriver circuits such as by providing a solution that can help reduceringing in SiC FETs without inhibiting the high speed and low energyloss operation of these devices.

High voltage switching circuits, such as circuits used in powerconverters, can use a control circuit, such as a gate driver, to controlthe switching characteristics of a switching device, such as a powertransistor that is configured to switch high power signals. In anexample, the switching characteristics of a switching device can becontrolled to convert a first power source that is generated by a firstcircuit to a second power source that is usable by another circuit. Theefficiency of a power converter, or the power conversion process, can becharacterized in terms of the amount of power loss during theconversion. The switching characteristics of the switching device, suchas a switching speed and slew rate, and physical characteristics of thedevice, such as its “on” resistance, can affected the amount of powerloss during a conversion process or during other switching operations.SiC FETs are useful as switching devices in power conversion circuit orother power switching applications, because these transistors exhibit,among other things, fast switching times, low parasitic capacitance, andrelatively small on resistance.

For example, a gate driver can actuate a SiC FET, or other power FET bygenerating a signal to control a pullup circuit to drive a current intothe gate of the transistor. The current charges the gate capacitance ofthe SiC FET to a threshold voltage to turn on the transistor. Similarly,a gate driver can actuate a SiC FET by generating a signal to control apulldown circuit to sink a current from the gate of the transistor todischarge the gate capacitance, thereby turning off the transistor. Thedrain voltage of a SiC FET can experience a high rate change as thetransistor is switched on or off. The changes or fluctuations in thedrain voltage can be capacitively coupled, such as though the Millereffect, to the gate of the SiC FET and can manifest as ringing in thegate voltage. Such ringing can damage or degrade the operation of theSiC FET or circuits coupled to the transistor. Techniques for mitigatingthe damaging effect of such ringing can include using active clampingcircuits or snubber circuits. These techniques, however, can degrade theperformance of SiC FETs, such as by causing increased power loss orreduced switching speeds.

Examples of the present disclosure can include techniques (e.g.,circuits, devices, systems, and methods) for reducing or preventingringing at the gate of a SiC FET such as by temporarily reversing theflow of a current out of the gate of the SiC FET when the transistor isdriven to turn off by a gate driver. In an example, a gate driver cangenerate a first control signal, such as a logical high signal orvoltage, to control a pullup circuit to turn on a SiC FET, such as bycausing the pullup circuit to drive a current into the gate of thetransistor until the voltage on the gate exceeds a threshold turn onvoltage. In an associated operation, the gate driver can generate asecond control signals, such as a logical low signal or voltage, tocontrol a pulldown circuit to turn the SiC FET off, such as by causingthe pulldown circuit to sink a current from the gate of the SiC FETuntil the voltage on the gate falls below a threshold turn off voltage.The gate driver can be improved by a booster circuit that can beconfigured to drive a current into the gate terminal of the SiC FETuntil the gate to source voltage (Vgs) of the SiC FET falls below athreshold voltage. Responsive to Vgs falling below the thresholdvoltage, the booster circuit can stop driving the current into the gateof the SiC FET and can allow the gate driver (e.g., the pulldowncircuit) to reverse the flow of current to the gate so as to sinkcurrent from the gate terminal to turn the transistor off with reducedor eliminated ringing in the gate voltage of the transistor.

FIG. 1 illustrates an example of a device 100 that is configured toattenuate ringing caused by feedback of an electrical signal at atransistor. The ringing may be generated at the gate terminal of a SiCFET by transient components of a high voltage signal (e.g., a 1000Vsignal) at the drain terminal of the transistor responsive to switchingthe transistor on or off. Such transients can exhibit large changes involtage with respect to time, which can damage or degrade the operationof SiC FET. The device 100 can include control circuit 105, boostercircuit 110, output circuit 115, and FET M2. The device 100 can alsoinclude a voltage divider circuit, such as a voltage divider formed byresistors R3 and R4, or any other suitable circuit for generating areference voltage V_(REF). The control circuit 105 can be connected tothe booster circuit 110. The booster circuit 110 can be connected to theoutput circuit 115, and the output circuit 115 can be connected to M2.The control circuit 105, the booster circuit 110, and the output circuit115 can be included in an integrated circuit, while M2 can be includedin another circuit that is external to the integrated circuit.

The device 100 can represent an element of a switching circuit or systemin which a control signal, such as a low current signal driven by anoutput of a microcontroller or other logic circuit, is used to drive aload, such as the gate capacitance of M2. Such switching circuits canuse a gate driver, such as the gate driver circuit formed by thecombination of control circuit 105, booster circuit 110, output circuit115, or other suitable power amplifier circuit as an interface betweenthe control signal and the load.

The FET M2 can include any FET or other transistor that is driven by agate driver. In an example, M2 is a power transistor, such as a SiC FET.

The control circuit 105 can include any circuit that is configured toreceive an input signal, such as lower-power or low current signal, andgenerate one or more control signals to controllably turn on and turn M2off. For example, the control circuit 105 can include the controlcircuit of a MOSFET, or other power transistor, gate driver circuit. Thecontrol circuit 105 can include a FET gate driver circuit. The one ormore control signals can include a first signal S1 that is configured toturn M2 on and a second signal S2 that is configured to turn M2 off. Inan example, S1 and S2 can be coupled to the booster circuit 110 such asby resistors R1 and R2. The resistors R1 and R2 can include the outputresistance of the control circuit 105 and may be configured in parallelto share current. The resistors R1 and R2 can be indicative of the highoutput impedance of the control circuit 105. In an example, the outputimpedance (e.g., a built-in impedance) is approximately 1 ohm. Thisindicates the minimum drive impedance is limited to that of the controlcircuit 105. In an example, S1 and S2 operate as a single control signalthat is driven to a positive voltage that is suitable for turning on thebipolar transistor Q1 so as to turn M2 on. The S1 and S2 can also bedriven to a low voltage that is suitable for turning on the bipolartransistor Q2 and turning off Q1, so as to turn M2 off. In anotherexample, S1 and S2 operate as distinct control signals such that S1 isdriven to a high voltage while S2 is placed in a high impedance state toturn M2 on. In this example, S2 can be driven to a low voltage while S1is placed in a high impedance state to turn M2 off.

The booster circuit 110 can include any circuit that can be configuredto detect a control signal, such as S2, to turn M2 off and, in responseto detecting the control signal, drive a current into the gate of M2 fora span of time before allowing the gate of M2 to discharge and turn offthe transistor. In an example, the booster circuit 110 can includeamplifiers 120 and 125, FET M1, protection diode D1, current limitingresistors R5 and R7, and auto-off resistor R6.

Amplifiers 120 and 125 can each include an operational amplifier, adifferential amplifier, a comparator, or similar circuit. Amplifiers 120and 125 can be configured to transition from providing high outputs,such as voltage close to a positive supply rail of the amplifiers, toproviding low outputs, such as a voltage at a negative or low supplyrail of the amplifiers, responsive to a voltage at their non-invertinginputs falling below a reference voltage V_(REF). In an example, thereference voltage V_(REF) is determined by the voltage divider formed byR3 and R4. In another example, V_(REF) is determined by any othersuitable circuit, such a bandgap reference circuit, that is configuredto provide a reference voltage. The amplifiers 120 and 125 can beconfigured so that their combined circuit provides sufficient current,output voltage, and switching speed to drive Q2 and M1 according tooperational specification of the device 100. Additionally, theamplifiers 120 and 125 can be configured so that the amplifier 125transitions from providing a high output, such as while the S1 isactuated or driven high, to providing a low output, such as after S2 isactuated or driven low, after a predetermined delay (hereinafter,“switching delay”). The switching delay is determined by the internaldelays of amplifiers 120 and 125, the time it takes S2 to fall belowV_(REF), and by switching or propagation delays of one or more othercomponents of the device 100.

The FET M1 can include any FET or any circuit that is configured toactuate the pullup circuit formed by Q1 to drive a current into the gateof M2 under the control of S1 and the output of amplifier 125.

The protection diode D1, the current limiting resistors R5 and R7, andthe auto-off resistor R6, can each be selected using any suitabletechnique to limit noise generated by high speed switching, protect M1and Q2 from damage, or to ensure the stable operation of the device 100.

The output circuit 115 can include any circuit that is configured todrive, responsive to actuation of S1 and S2 by the control circuit 105,a current into the gate of M2 so as to turn on the transistor. Theoutput circuit 115 can include any circuit that is configured to sink asufficient current from the gate of M2 to turn off the transistor. Theoutput circuit 115 can include a pullup circuit, such as the pullupcircuit formed by Q1, and a pulldown circuit such as the pulldowncircuit formed by Q2. The output circuit 115 can include a flybackprotection circuit, such as a circuit formed by resistors R8 and R9 anddiodes D2 and D3. The resistors R8 and R9 and the diodes D2 and D3 canbe selected using any suitable technique.

In an example of operation of the device 100, the reference voltageV_(REF) is lower than the actuated voltage of S1 and higher than thethreshold voltage for turning M2 off. For example, the operation of thedevice 100 can be characterized to determine a value of V_(REF) thatattains a target amount of ripple suppression at the gate of M2. Suchcharacterization can include operating the device 100 while adjustingthe ratio of R3 to R4 until a sufficient ripple suppression is obtainedat the gate of M2 or until a suitable switching delay is determined. Inan example, a value of V_(REF) can be determined from predeterminedcharacterization information for the device 100.

In operation, the control circuit 105 provides a first output signal,such as S1, to turn M2 on. Providing such output signal can includetri-stating S2, such as by assigning S2 a high impedance signal or valueand driving S1 high. The cascaded combination of amplifiers 120 and 125turns Q2 off and turns M1 on. The FET M1, in the on state, couples S1 tothe gate of Q1, which turns Q1 on. The bipolar transistor Q1 drives acurrent from the power source V_(CC) into the gate of M2 to turn on theFET. The control circuit 105 can provide a second output signal, such asS2, to turn M2 off. Providing the second output signal can includetri-stating S1 and driving S2 low. Although the control circuit 105drives S2 low, it takes finite amount of time for the voltage on net 130to fall. The output of each of amplifiers 120 and 125 will be high for atime (e.g., a first delay), including the time it takes the voltage onnet 130 (e.g., S1) to fall below V_(REF). After the voltage on net 130falls below V_(REF), the output of amplifier 120 will go low after adelay (e.g., 20 nanosecond, ns, delay) determined by the internalcircuit or propagation delay of amplifier 120. After another delay(e.g., a third delay) determined by the internal circuit of amplifier125 (e.g. another 20 ns), the output of amplifier 125 goes low. The FETM2 begins to turn off during the span of time including the first delay,the second delay, and the third delay. The booster circuit 110 keeps M1turned on during this span of time, causing current to be driven thoughQ1 into the base of M2. The FET M1 turns off a short time afteramplifier 125 turns off, thereby inhibiting the flow of current into thegate of M2 and allowing M2 to fully turn off by discharging the chargeon the gate of M2 through Q2. The current driven into the gate of M2while M2 begins to turn off, reducing ringing at the gate of M2 when theFET is turned off.

FIGS. 2A and 2B illustrate an example of ringing caused by feedback ofan electrical signal at a transistor, such as the FET M2 shown inFIG. 1. FIG. 2A shows a diagram of the drain voltage 205 of thetransistor, while FIG. 2B shows a diagram of the gate voltage of thetransistor. As shown in the figures, the ringing 225 at the gate of thetransistor is caused by transients 210 at the drain of transistor, fedback to the gate, in the frequency range of approx. 30 Mhz. In anexample, the transients 210 are high voltage transients generated byoperating the transistor to switch a high voltage signal, such a drainvoltage 205 having a magnitude of 1200V, at a high speed, such as at 3ns switching times or periods. In an example, the high output impedanceof a driver circuit, such as an impedance of one ohm or greater outputimpedance of the control circuit 105, makes it difficult prevent orlimit the ringing 225.

FIGS. 3A, 3B, and 3C illustrate an example of attenuated ringing at atransistor, such as using the techniques described herein. In anexample, the transistor is a FET, such as M2. FIG. 3A depicts a plot ofrising drain voltage 305 as the transistor is switched off superimposedover a plot of falling drain voltage 310 as the transistor is switchedon. FIG. 3B depicts a plot of current at the gate of the transistor whenthe transistor is switched off 315 superimposed over a plot of currentat the gate of the transistor when the transistor is switched on 320.FIG. 3C depicts a plot of falling gate voltage 325 as the transistor isswitched off superimposed over a plot of rising gate voltage 330 as thetransistor is switched on. The transistor described in FIGS. 3A, 3B, and3C is operated under substantially similar conditions as the transistordescribed in the discussion of FIGS. 2A and 2B, with the exception thatthe transistor described in FIGS. 3A, 3B, and 3C is driven to turn offas described herein. In an example, the transistor is driven accordingto the device 100, such that a current 340 is driven into the gate ofthe transistor for a short time after the transistor is actuated orcommanded to turn off by the control circuit 105. As shown in FIGS. 3A,3B, and 3C, transients 335 at the drain of the transistor are suppressedat, or are not coupled to, the gate of the transistor. The suppressionof such transients is indicative of reduced ringing at the gate of thetransistor. Such reduced ringing is caused by temporarily drivingcurrent into the gate of the transistor after the transistor iscommanded to turn off but before the device actually turns off, such asdescribed herein.

FIG. 4 illustrates an example of a device 400 that includes a switchingcircuit that is configured to reduce ringing caused by feedback of anelectrical signal at a transistor. In an example, the device 400includes one or more components of the device 100 shown in FIG. 1. In anexample, the device 400 includes control circuit 405 that is analogousto the control circuit 105, a booster circuit 410 that is analogous tothe booster circuit 110, and an output circuit that is analogous to theoutput circuit 115. In an example, the device 400 also includes atransistor 420 that is analogous to the FET M2. In an example, thetransistor 420 is a power transistor, such as a SiC FET.

The control circuit 405 can include any circuit that is configured togenerate one or more control signals, such as S1 and S2 of FIG. 1, toturn the transistor 420 on or to turn the transistor 420 off.

The booster circuit 410 can include any circuit that is configured todetect a control signal from the control circuit 405 to turn thetransistor 420 off and, responsive to detecting the signal, temporarilydrive a current into the gate of the transistor 420, such as for a timedetermined by the amount of time it takes for the control signal or thevoltage on the gate of the transistor 420 to fall below a thresholdvoltage. The threshold voltage can be determined by characterizing theoperation of the device 400 for a specific application, such as for aspecific configuration of the components of the device 400, a switchingrate of the transistor 420, or a signal switched by the transistor. Thebooster circuit 410 can include a drive circuit 425, a delay circuit430, and a sensing circuit 435. The drive circuit 425 can include one ormore circuits that are configured to control the output circuit 415,such as by providing a current to drive the pullup circuit 440 and thepulldown circuit 445, to temporarily drive the current into the gate ofthe transistor 420. The drive circuit 425 can include the FET M1 andsupporting circuitry. The delay circuit 430 can include one or morecircuits that are configured to determine the amount of time duringwhich current is driven into the gate of the transistor 420, such asafter the control circuit commands the transistor to turn off. In anexample, the delay circuit 430 includes at least the amplifier 120 or125 and a voltage reference circuit, such as the voltage divider formedby resistors R3 and R4. The sensing circuit 435 can include one or morecircuits that are configured to detect the control signal or the voltageat the gate of transistor 420 falling to or below a threshold voltage,such as described herein. The sensing circuit 435 can include thevoltage divider formed by R3 and R4, and the amplifier 120 or 125, asshown in FIG. 1.

The output circuit 415 can include any circuit that is configured tosource or sink sufficient current to turn transistor 420 on or to turntransistor 420 off. The output circuit 415 can include a pullup circuit440, such as formed by Q1 in FIG. 1, and pulldown circuit 445, such asformed by Q2.

FIG. 5 illustrates an example of a set of operations 500 such as foroperating a circuit to attenuate or reduce ringing caused by feedback ofan electrical signal at a transistor. The transistor can include a powertransistor, such as SiC MOFSET such as the FET M2 showing in FIG. 1 orthe transistor 420 shown in FIG. 4. The operations 500 can be executedor implemented in any of the techniques described herein.

At 505, a control signal, such as the signal S2 that is generated by thecontrol circuit 105 in FIG. 1, can be detected. The control signal canbe configured to switch the transistor from an on-state to an off-state.At 510, responsive to detecting the control signal, a first current canbe driven into a gate (or other control terminal) of the transistor. Thefirst current can be driven into the gate terminal while a voltage onthe gate terminal is higher than a first threshold voltage. The firstthreshold voltage can be a voltage at which a sufficient amount currentis driven into the gate terminal to reduce ringing at the gate below athreshold voltage level. Driving the first current into the gateterminal can include driving the first current into the gate terminalfor an indicated span of time after detecting the control signal orafter the control signal is actuated. The indicated span of time can beselected to allow enough time for the voltage on the gate terminal tofall below the first threshold voltage. The indicated span of time, orthe tolling of the indicated span of time, can be at least partiallydetermined, or triggered based, on detecting the voltage of the controlsignal fall below a second threshold voltage. At 515, a second currentcan be sunk from the gate terminal to turn the transistor off. Forexample, the second current can be sunk responsive to expiration of theindicated span of time. In an example, the second current is sunkresponsive to detecting that the voltage on the gate terminal of thetransistor is below the first threshold voltage.

The set of operations 500 can include any other operation that issuitable for implementing the techniques described herein.

Each of the non-limiting aspects above can stand on its own or can becombined in various permutations or combinations with one or more of theother aspects or other subject matter described in this document.

The above detailed description includes references to the accompanyingdrawings, which form a part of the detailed description. The drawingsshow, by way of illustration, specific embodiments in which embodimentsof the invention can be practiced. These embodiments are also referredto generally as “examples.” Such examples can include elements inaddition to those shown or described. However, the present inventorsalso contemplate examples in which only those elements shown ordescribed are provided. Moreover, the present inventors also contemplateexamples using any combination or permutation of those elements shown ordescribed (or one or more aspects thereof), either with respect to aparticular example (or one or more aspects thereof), or with respect toother examples (or one or more aspects thereof) shown or describedherein. In the event of inconsistent usages between this document andany documents so incorporated by reference, the usage in this documentcontrols.

In this document, the terms “a” or “an” are used, as is common in patentdocuments, to include one or more than one, independent of any otherinstances or usages of “at least one” or “one or more.” In thisdocument, the term “or” is used to refer to a nonexclusive or, such that“A or B” includes “A but not B,” “B but not A,” and “A and B,” unlessotherwise indicated. In this document, the terms “including” and “inwhich” are used as the plain-English equivalents of the respective terms“comprising” and “wherein.” Also, in the following claims, the terms“including” and “comprising” are open-ended, that is, a system, device,article, composition, formulation, or process that includes elements inaddition to those listed after such a term in a claim are still deemedto fall within the scope of that claim. Moreover, in the followingclaims, the terms “first,” “second,” and “third,” etc. are used merelyas labels, and are not intended to impose numerical requirements ontheir objects.

Method examples described herein can be machine or computer-implementedat least in part. Some examples can include a computer-readable mediumor machine-readable medium encoded with instructions operable toconfigure an electronic device to perform methods as described in theabove examples. An implementation of such methods can include code, suchas microcode, assembly language code, a higher-level language code, orthe like. Such code can include computer readable instructions forperforming various methods. The code may form portions of computerprogram products. Further, in an example, the code can be tangiblystored on one or more volatile, non-transitory, or non-volatile tangiblecomputer-readable media, such as during execution or at other times.Examples of these tangible computer-readable media can include, but arenot limited to, hard disks, removable magnetic disks, removable opticaldisks (e.g., compact disks and digital video disks), magnetic cassettes,memory cards or sticks, random access memories (RAMs), read onlymemories (ROMs), and the like.

The above description is intended to be illustrative, and notrestrictive. For example, the above-described examples (or one or moreaspects thereof) may be used in combination with each other. Otherembodiments can be used, such as by one of ordinary skill in the artupon reviewing the above description. The Abstract is provided to complywith 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain thenature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the scopeor meaning of the claims. Also, in the above Detailed Description,various features may be grouped together to streamline the disclosure.This should not be interpreted as intending that an unclaimed disclosedfeature is essential to any claim. Rather, inventive subject matter maylie in less than all features of a particular disclosed embodiment.Thus, the following claims are hereby incorporated into the DetailedDescription as examples or embodiments, with each claim standing on itsown as a separate embodiment, and it is contemplated that suchembodiments can be combined with each other in various combinations orpermutations. The scope of embodiments of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

The claimed invention is:
 1. A switching circuit to reduce electricalfeedback ringing at a gate terminal of a transistor, the switchingcircuit comprising: a transistor circuit to switch an electrical signal;a control circuit to provide an actuation signal to the gate terminal ofthe transistor circuit; and a booster circuit that is disposed betweenthe control circuit and the gate terminal of the transistor circuit, thebooster circuit arranged to: detect a signal from the control circuit toturn off the transistor circuit; and responsive to the detected signal;drive a first current into the gate terminal of the transistor circuitfor a specified span of time before the transistor circuit turns off,and sink a second current from the gate terminal of the transistorcircuit responsive to expiration of the specified span of time.
 2. Theswitching circuit of claim 1, further comprising: a delay circuit thatis configured to determine the specified span of time based on thedetected signal and a reference signal.
 3. The switching circuit ofclaim 2, wherein the delay circuit comprises an amplifier circuit thatis configured to compare the detected signal to the reference signal andgenerate a delay signal to control the current driven into the gateterminal of the transistor.
 4. The switching circuit of claim 3, furthercomprising: an output stage comprising a pullup circuit and a pulldowncircuit; and a second transistor that is configured to couple theactuation signal that is generated by the control circuit to a controlterminal of the pullup circuit, the second transistor actuated by thedelay signal generated by the amplifier circuit.
 5. The switchingcircuit of claim 4, wherein the output stage further comprises apulldown circuit that is configured to sink a current from the gateterminal of the transistor, the pulldown circuit actuated by the delaysignal generated by the amplifier circuit.
 6. The switching circuit ofclaim 1, wherein the transistor is a field effect transistor (FET) thatis configured to switch a signal of that has a voltage amplitude ofleast 1000 volts.
 7. The switching circuit of claim 1, wherein thetransistor is a silicon carbide device FET.
 8. A method for controllinga field effect transistor (FET) to reduce electrical feedback ringing ata gate terminal of the FET, the method comprising: detecting a controlsignal to switch the FET from an on-state to an off-state; driving,responsive to detecting the control signal, a first current into thegate terminal while a voltage on the gate terminal is greater than anindicated threshold voltage; and sinking a second current from the gateterminal to turn off the FET responsive to the voltage on the gateterminal falling below the indicated threshold voltage.
 9. The method ofclaim 8, wherein driving the first current into the gate terminal whilea voltage on the gate terminal is greater than an indicated thresholdvoltage comprises driving the first current into the gate terminal foran indicated span of time, the indicated span of time being at leastlong enough to enable the voltage on the gate terminal to fall below theindicated threshold voltage.
 10. The method of claim 9, furthercomprising determining the indicated span of time based on detecting avoltage of the control signal falling below a second threshold voltage.11. The method of claim 9, further comprising determining the indicatedspan of time based on a propagation delay though a least an amplifiercircuit or a comparator circuit.
 12. The method of claim 9, whereinsinking the second current from the gate terminal to turn off the FETresponsive to the voltage on the gate terminal falling below theindicated threshold voltage comprises controlling a pulldown circuit tosink the second current from the gate terminal into a negative rail of apower source responsive to expiration of the indicated span of time. 13.The method of claim 8, wherein sinking the second current from the gateterminal to turn off the FET responsive to the voltage on the gateterminal falling below the indicated threshold voltage comprises:detecting the voltage on the gate terminal fall below the indicatedthreshold voltage; and controlling, responsive to detecting the voltageon the gate terminal fall below the indicated threshold voltage, apulldown circuit to sink the second current from the gate terminal intoa power supply rail.
 14. The method of claim 8, wherein driving thefirst current into the gate terminal while a voltage on the gateterminal is greater than an indicated threshold voltage comprisescontrolling a pullup circuit to drive the first current into the gateterminal from a positive rail of a power source.
 15. A system forreducing electrical feedback ringing a gate terminal of a field effecttransistor (FET), the system comprising: means for detecting a controlsignal to switch the FET from an on-state to an off-state; means fordriving, responsive to detecting the control signal, a first currentinto the gate terminal while a voltage on the gate terminal is at leastas high as an indicated threshold voltage; and means for sinking asecond current from the gate terminal to turn off the FET responsive tothe voltage on the gate terminal falling below the indicated thresholdvoltage.
 16. The system of claim 15, further comprising: means fordetermining that the voltage on the gate terminal is below the indicatedthreshold voltage.
 17. The system of claim 16, wherein the means fordetermining that the voltage on the gate terminal is below the indicatedthreshold voltage comprises means for determining a span of time fordriving the first current into the gate terminal.
 18. The system ofclaim 16, further comprising: means for controlling, responsive todetecting the voltage on the gate terminal fall below the indicatedthreshold voltage, a pulldown circuit to sink the second current fromthe gate terminal into a power supply rail.
 19. The system of claim 15,wherein the means for driving the first current into the gate terminalwhile a voltage on the gate terminal is greater than the indicatedthreshold voltage comprises means for controlling a pullup circuit todrive the first current into the gate terminal from a positive rail of apower source.